The present invention relates to the reading of a memory such as a flash memory and, more particularly, to the generation of soft bits, e.g. for error correction, during such reading.
Flash memory devices have been known for many years. NAND-type flash memories differ from other types of flash memories (e.g. NOR), among other specific characteristics, by the fact that a certain number of information bits, written to the memory, may be read back “flipped”, i.e. different from what these bits were as originally written to the memory.
In order to overcome this phenomenon and to make NAND memories usable by real applications, it is common to use Error Correction Codes (ECC) in conjunction with these memories. The following is a general principle of using ECC in Flash memories:
Before writing data to the memory, an ECC algorithm is applied to this data in order to compute additional (redundant) bits that are later used for error detection and correction. These redundant bits are often called “parity bits” or “parity”, and a combination of the original data and the parity is called a “codeword”.
The entire codeword (i.e. the original data and the parity) is recorded to the flash memory. It should be noted that the actual size of the NAND Flash memory is larger than the size of the original (application) data, and the NAND flash memory is designed to accommodate parity as well as the original data.
When the data are retrieved from the memory, the entire codeword is read, and an ECC algorithm is applied to the data and the parity in order to detect and correct possible “bit flips” (i.e., errors).
It should be noted that the implementation of the ECC may be done by hardware, by software or by a combination of hardware and software. Furthermore, ECC may be implemented within a memory, within a memory controller, within a host computer, or may be “distributed” among these parts of a system.
Most ECC algorithms that are used in conjunction with NAND Flash memories use the information stored in the memory device (both data and parity) for both detection of errors and correction of errors. The same number of information bits that were written to the memory are read out of the memory and are used for ECC calculations and decisions. This information is sometimes called “Hard Bits”, to indicate a “hard” connection between the written data and the read data.
It is well known that the data stored in Flash memory is actually represented by certain discrete threshold voltage levels of memory cells. So, in Single Level Cell (SLC) devices, that store one bit per memory cell, actual data are represented by one of two threshold voltage levels per cell; in Multi-Level Cell (MLC) devices that store two bits per cell, actual data are represented by one of four threshold voltage levels per cell; and, generally, in MLC devices that store “n” bits in each cell, actual data are represented by one of 2n threshold voltage levels per cell.
The process of reading data from a Flash memory cell consists of comparing the cell voltage to a set of pre-defined reference voltages, with a logical combination of the results of these comparisons determining the data as read from the cell. In standard Flash devices, storing “n” bits per cell, the number of such comparisons is 2n−1.
Because reference voltages are discrete, a cell of certain threshold voltage level has a data value assigned to this level. This is regardless of the actual cell threshold voltage, which may vary between the lower reference voltage and the upper reference voltage of a threshold voltage band that corresponds to the data value. Therefore, in the case of error, the cell threshold voltage value, as read from the Flash memory, may provide absolutely NO information about the possible original value of the cell threshold voltage level as written.
However, it is clear that if a cell's actual threshold voltage is closer to a lower reference voltage than to a higher reference voltage, then the probability of this cell representing a “lower” value is higher than the probability of the cell representing a “higher” value, and vice versa.
Let us consider, for example, two-bit-per-cell MLC device with the following reference voltage bands:
Band 0 (Erase)—<0 V
Band 1—between 0 V and 1.5 V
Band 2—Between 1.5 V and 3 V
Band 3—above 3 V
In this device, a cell with a threshold voltage of 1.6 V is read as cell of Band 2, but has a higher probability of being originally of Band 1 than of being originally in Band 3. Similarly, a cell with a threshold voltage of 1.3 V, read as Band 1, has a higher probability of being originally in Band 2 than of being originally in the Erase state.
It is well known from Information theory that the more information available for the decision making, the more efficient and accurate is the decision making process. In our case, the more information we have on the cell state (cell threshold voltage, actually), the more efficient and accurate the error detection and correction algorithms will be.
From the above discussion it is clear, that in order to enhance ECC efficiency, more information on a cell threshold voltage than a “standard” reading of a cell state should be obtained. This is done by performing comparisons of a cell threshold voltage to additional reference voltages and thus reading of additional so called “soft” information (or “soft” bits) from the memory device. Considering the above mentioned example of two-bit-per-cell MLC Flash, comparison of a cell threshold voltage with additional reference voltages of, say, −0.75 V, 0.75 V, 2.25 V and 3.75 V (in addition to the “standard” 0, 1.5 and 3 V) generates one additional soft bit for each cell—a bit that then may be used in an enhanced ECC mechanism. Using a more “refined” set of reference voltages may, of course, generate additional soft bits in the device.
The use of soft bits in ECC is not new in the art. Consider for example U.S. Pat. No. 7,023,735, “METHODS OF INCREASING THE RELIABILITY OF A FLASH MEMORY” to Ban et al., which is incorporated by reference for all purposes as if fully set forth herein. This patent describes the use of soft bits, read from a Flash memory device, to enhance an ECC mechanism and so to increase Flash memory reliability.
However, in order to obtain these soft bits from the memory device, the device has to contain, in addition to support for additional reference voltages, lots of logic circuitry, control mechanisms to support additional reading (i.e. additional comparison cycles), as well as data registers to hold intermediate reading results. All these make the memory device more complicated and less optimal in the utilization of silicon, because the design of the internal structure of a Flash memory chip is optimized for memory cells, rather than for logic circuits.
There is thus a widely recognized need for, and it would be highly advantageous to have, a method of reading soft bits from a flash memory device designed for reading only hard bits, without substantial modification of the flash memory device.
The present invention is described below with reference to the prior art flash memory devices illustrated in FIGS. 1 and 2.
FIG. 1, that is modified from FIG. 1 of Guterman et al., U.S. Pat. No. 6,751,766, shows a self-contained flash memory device 10 that includes an array 12 of individually addressable flash memory cells arranged in a regular array of rows and columns. Individual memory cells are controlled by bit lines, select gates arranged in word lines, and steering gates. Bit lines extend along columns of array 12. Word lines extend along columns of array 12. A bit line unit 14 includes a bit line decoder, storage elements, driver circuits and sense amplifiers. Bit line unit 14 is coupled to array 12 by a line 16 and to a controller 18 by a bit-control line 20 and by a read line 22. A word line unit 24 includes a select gate decoder and driver circuits. Word line unit 24 is coupled to array 12 by a line 26 and to controller 18 by a word-control line 28. A steering unit 30 includes a steering gate decoder and driver circuits. Steering unit 30 is coupled to array 12 by a line 32, to controller 18 by a steering-control line 34 and to bit line unit 14 by a-line 36. Bit line unit 14, word line unit 24 and steering unit 30 collectively constitute the memory cell management circuitry 46 of device 10. Bit line unit 14, word line unit 24 and steering unit 30 are coupled to a bus 38 that in turn is coupled to controller 18. Controller 18 is coupled to a host 40 of device 10 by a line 42.
When a preselected memory cell is to be read, voltages are applied to the corresponding bit lines, word line and steering gates, corresponding to the preselected memory cell, at predetermined levels sufficient to enable the reading of the preselected memory cell. Controller 18 applies voltages of the bit lines through bit-control line 20. Controller 18 applies voltages of the word line through word-control line 28. Controller 18 applies voltages of steering gates through steering-control line 34. A current is generated through the preselected memory cell by these voltages. The current is indicative, in a SLC device 10, of whether or not the preselected memory cell was programmed, and in a MLC device 10, of which of the reference voltage bands the memory cell was programmed to. The value of the current is amplified and compared to reference currents by sense amplifiers in bit line unit 14. The results of the comparison are stored temporarily in latches or registers. The resultant data, read out from the preselected memory cell, are sent to controller 18 through read line 22.
FIG. 2 is a high-level partial block diagram of a data storage system 50 that includes a flash memory device 48. Data storage system 50 also includes a processor 52 and three more memory devices: a RAM 54, a boot ROM 56 and a mass storage device 58. Processor 52 and memory devices 48, 54, 56 and 58 communicate with each other via a common bus 66. Like flash memory device 10, flash memory device 48 includes a flash memory cell array 62 and memory cell management circuitry 60. Unlike flash memory device 10, flash memory device 48 lacks its own controller. Instead, processor 52 emulates controller 18 by executing an appropriate software driver that is stored in mass storage device 58 and that is loaded into RAM 54 for execution. Flash memory device 48 also includes a bus interface 64 to enable processor 52 to communicate with memory cell management circuitry 60.